The present invention relates generally to a system for conserving power and increasing performance in a portable computer. More particularly, this invention relates to a system for reducing the number of wait states in a portable computer by adding an external cache memory comprised of SRAM circuits, in addition to any internal cache memory that may be provided in the main microprocessor. Still more particularly, this invention relates to a portable computer that includes a secondary cache that can be powered up for increased computational performance, and powered down during periods of inactivity to conserve power.
Data is transferred between the central processing unit ("processor" or "CPU") of the computer and conventional system memory in two steps. First, the CPU generates signals on the address bus representing the address of the desired memory location. At the next, or at subsequent, clock cycles, the CPU actually transfers data on the data bus to or from the addressed memory location. For the microprocessors in the INTEL 8086.RTM. family, the number of cycles for the CPU to access data in memory depends upon the processor and the speed of the memory unit.
Memory circuits comprise two general types: (1) static random access memory ("SRAM") circuits, and (2) dynamic random access memory ("DRAM") circuits. SRAM circuits are operable at very high speeds, matching the operating speed of high-end microprocessors. DRAM circuits, conversely, are slower and cannot match the speed of these microprocessors. SRAM circuits, however, are more expensive than DRAM circuits, and require much more space for the same amount of storage capacity.
The speed of memory circuits is based upon two timing parameters. The first parameter is memory access time, which is the minimum time required by the memory circuit to set up a memory address and produce or capture data on or from the data bus. The second parameter is the memory cycle time, which is the minimum time required between two consecutive accesses to the memory circuit. For SRAM circuits, the access time typically is equal to the cycle time. SRAM circuits are commercially available with cycle times of at least 30-40 nanoseconds. For DRAM circuits, conversely, the cycle time typically is twice the access time. Dram circuits have an access time in the range of 60-100 nanoseconds, with cycle times of 120-200 nanoseconds. The extra time required for consecutive memory accesses in a DRAM circuit is necessary because the internal memory circuits require additional time to recharge to accurately produce data signals. In addition, DRAM circuits also require periodic refresh cycles to protect the integrity of the stored data. These cycles consume approximately 5 to 10% of the time available for memory access.
Because of these limitations, memory constructed with DRAM circuits is not always capable of responding to memory accesses within the time interval allotted by the CPU. In this event, external circuitry must signal to the CPU that supplementary processor cycles, or wait states, are necessary before the dam is ready on the data bus, or before data from the data bus has been stored by the memory circuits. In addition to slowing the processing of the CPU, wait states require use of the bus, thereby limiting access to the bus by other system circuitry.
As the operating speed of processors increase and as new generations of processors evolve, it is obviously advantageous to minimize wait states to fully exploit the capabilities of these new processors. Implementing these new generation of high speed processors in portable computers, however, is especially difficult, because of size and power limitations. In particular, the use of SRAM circuits to reduce the number of wait states has not been considered a viable alternative because of the power consumption of these types of circuits. Consequently, it is extremely difficult to design a system that reduces wait states in portable computers that implement the new high speed processors.
In the past, several alternative designs have been used to deal with this problem of wait states in personal computers. The simplest and least expensive design is to use standard DRAM circuits as the system (or main) memory, and accept the reduction in processing speed caused by the relatively large number of wait states. This method obviously results in an inefficient system, with an uneven performance level between the CPU and the memory system.
Another design uses more expensive, faster DRAM circuits as the system memory, that reduces the number of wait states to some limited extent. Even with fast DRAM circuits, however, the access time is not sufficiently short to eliminate wait states when high speed processors are implemented.
A third approach is to use SRAM circuits as the system memory. SRAM circuits, as noted, typically have a cycle time that is approximately equal to the access time. While this method is an effective solution to the problem of wait states, it is a solution that is very expensive, and requires a large amount of space and power. Because of space and power limitations in portable computers, SRAM circuits are not a viable alternative for system memory in these computers.
None of the above methods have proven to be a cost effective solution to the problem of wait states, especially in the context of portable computers. A hybrid approach, however, has been found and used extensively for reducing the number of wait states, particularly in desktop computers where power is not a critical design parameter. This technique commonly is referred to as memory caching. A memory cache is used in combination with a standard DRAM system memory to reduce the number of wait states. As shown in FIG. 1, the memory cache typically comprises a buffer of fast SRAM circuits placed between the CPU and main memory. The high speed memory cache is used to store recently accessed addresses and data in the SRAM buffer, where further accessing of this data can occur without any additional wait states. The underlying principle is that most application programs will work within small sections of code and with a relatively small set of data.
Cache memory systems have been used extensively to increase the speed at which memory is retrieved by the CPU. The memory cache essentially comprises a fast intermediate memory buffer between the processing circuits of the CPU and the main memory of the computer, which is used as the working memory for the processor. Physically, a cache memory can be located internally to the microprocessor chip (as is done in the INTEL 80486.RTM. chip), or can be implemented through external memory and control circuits (as must be done with the INTEL 80386.RTM. chip).
Although an eight Kbyte on-chip memory cache unit is provided as part of the INTEL 80486.RTM. architecture, those skilled in the art have realized that the number of wait states could be further reduced by adding a secondary or supplementary memory cache external to the 80486 or other microprocessor, comprised of fast SRAM circuits. Such a secondary cache has been used in certain desktop computers to increase the performance level of the computer.